发明名称 CELL INFERIORITY TEST CIRCUIT
摘要 PURPOSE: A cell inferiority test circuit is provided to sufficiently secure a margin between a strobe signal and compressed data regardless of the change of processes, voltages, and temperature by including a test mode in which the delay period of the strobe signal is regulated. CONSTITUTION: A compressed data generating part(1) compresses selected data in response with a selection signal. The compressed data generating part generates compressed data including information related to the inferiority of cells. A delay strobe signal generating part(2) delays a strobe signal as much as a delay period, which is pre-set by a test signal, in order to generate a delay strobe signal. An input-output line driving part drives a global input-output line by receiving the compressed data.
申请公布号 KR20100107783(A) 申请公布日期 2010.10.06
申请号 KR20090026044 申请日期 2009.03.26
申请人 HYNIX SEMICONDUCTOR INC. 发明人 LEE, JOO HYEON
分类号 G11C29/40;G11C7/10;G11C8/00 主分类号 G11C29/40
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