发明名称 SINGLE-WIRE AND THREE-WIRE BUS INTEROPERABILITY
摘要 PROBLEM TO BE SOLVED: To enable interoperability between existing serial bus interfaces and a single-wire bus interface. SOLUTION: In one aspect, an output of a three-wire interface is selected in a first mode and outputs of one or more single-wire interfaces are selected in a second mode. In another aspect, a converter accepts a single-wire bus and produces signals according to a three-wire interface. In yet another aspect, a termination symbol is inserted in a single-wire interface signal, to facilitate conversion of a single-wire interface signal and connection to a three-wire interface. In yet another aspect, a strobe signal and/or a clock signal are generated in response to a detected start symbol. In yet another aspect, a strobe signal is deasserted and/or a clock signal is deasserted in response to a detected termination symbol. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010220222(A) 申请公布日期 2010.09.30
申请号 JP20100085242 申请日期 2010.04.01
申请人 QUALCOMM INC 发明人 HANSQUINE DAVID W;MUNEER MUHAMMAD ASIM
分类号 H04L29/06;G06F13/38;G06F13/42 主分类号 H04L29/06
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