| 摘要 |
PROBLEM TO BE SOLVED: To suppress the expansion of a cell layout area, while preventing wiring congestion. SOLUTION: A design method of a semiconductor integrated circuit has processes to be executed by a computer as follows: a virtual layout process for virtually laying out a layout area determined by a layout algorithm and a logical cell group laid out in the layout area; a concentration point detection process for detecting a concentrated point of logical cells having a set width or narrower in the layout area, based on the virtual layout process; a wiring index calculation process for calculating a wiring index of the concentrated point; an adjacent restriction reallocation process for virtually reallocating the logical cell group based on adjacent restriction when the wiring index is a set limit value or smaller; and an actual layout process for actually laying out the logical cell group in the layout area, based on the result of the adjacent restriction reallocation process. COPYRIGHT: (C)2010,JPO&INPIT
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