发明名称 THREE-DIMENSIONAL ELECTRONICS PACKAGE
摘要 An electronics package 100 comprising a substrate 105 having a planar surface 107, a memory die 110 and a logic die 120. Memory circuit components 112 interconnected to memory die contacts 114 located on an outer surface 116 of a face 118 of the memory die. Logic circuit components 122 interconnected to logic die contacts 124 located on an outer surface 126 of a face 128 of the logic die. Memory die contacts and the logic die contacts are interconnected such that the face of the memory die opposes the face of the logic die. A plurality of bonds 130 interconnect input-output contacts 132 on the planar surface of the substrate, to external die contacts 135 on one of the face of the logic die or the face of the memory die. One face opposes the planar surface, the other face is not directly connected to the interconnect input-output contacts.
申请公布号 US2010244276(A1) 申请公布日期 2010.09.30
申请号 US20100725169 申请日期 2010.03.16
申请人 LSI CORPORATION 发明人 BURLESON JEFFREY P.;MOINIAN SHAHRIAR;OSENBACH JOHN;PALLINTI JAYANTHI
分类号 H01L23/50;H01L21/60 主分类号 H01L23/50
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