| 摘要 |
<P>PROBLEM TO BE SOLVED: To increase an upper-limit operating frequency of a signal level conversion circuit. <P>SOLUTION: A level conversion circuit comprises: a first MOS transistor (MOS-Tr) receiving a clock signal in its gate (G) electrode; a second MOS-Tr connecting its drain (D) electrode to a D electrode of the first MOS-Tr; a third MOS-Tr receiving a clock signal of an inverse phase in its G electrode; a fourth MOS-Tr connecting its G and D electrodes to a G electrode of the second MOS-Tr and a D electrode of the third MOS-Tr; and an inverter circuit receiving signals extracted from the D electrodes of the first and second MOS-Trs. In the level conversion circuit, a plurality of fifth MOS-Trs connected in parallel are provided at least between the source electrode of the second MOS-Tr and a power source or between a source electrode of the fourth MOS-Tr and the power source, and a control circuit is provided for controlling conduction and shutoff of the fifth MOS-Trs in such a way that an average voltage of output of the inverter circuit becomes an intermediate voltage between low-potential side power supply and a high-potential side power supply. <P>COPYRIGHT: (C)2010,JPO&INPIT |
