发明名称 PATTERN LAYOUT, MANUFACTURING METHOD OF DUMMY PATTERN LAYOUT, PHOTOMASK, EXPOSURE TRANSFER METHOD, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
摘要 <p><P>PROBLEM TO BE SOLVED: To prevent a fault of disconnection or pattern collapse by obtaining a focus margin of a desired numerical value in the whole wiring pattern. <P>SOLUTION: In a pattern layout including a transmission region F and a light shielding region E and used for manufacture of a semiconductor, a dummy pattern G having such a size that resist resolution is impossible in a photolithography process of manufacture of the semiconductor is disposed in the transmission region where the focus margin is made smaller than the desired numerical value and the desired numerical value is such a value that the fault of disconnection or pattern collapse is generated when the focus margin is made smaller than the numerical value. <P>COPYRIGHT: (C)2010,JPO&INPIT</p>
申请公布号 JP2010217345(A) 申请公布日期 2010.09.30
申请号 JP20090061998 申请日期 2009.03.13
申请人 SHARP CORP 发明人 WATANABE KUNIO
分类号 G03F1/36;G03F1/68 主分类号 G03F1/36
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