| 摘要 |
The invention relates to a parallel processor which comprises elementary processors (3) disposed according to a topology with a predetermined position within this topology and capable of simultaneously executing the same instruction on different data, the instruction relating to at least one operand and/or providing at least one result. The instruction comprises, for each operand and/or each result, information relating to the position of a field of action within a data structure of the table of dimension M type and the parallel processor comprises means (41, 42, 43) for calculating the address of each operand and/or each result within each elementary processor, as a function of the position of the field of action and of the position of the elementary processor within the topology.
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