发明名称 Filp Chip Interconnection Structure with Bump on Partial Pad and Method Thereof
摘要 A semiconductor package includes a semiconductor die with a plurality of solder bumps formed on bump pads. A substrate has a plurality of contact pads each with an exposed sidewall. A solder resist is disposed opening over at least a portion of each contact pad. The solder bumps are reflowed to metallurgically and electrically connect to the contact pads. Each contact pad is sized according to a design rule defined by SRO+2*SRR−2X, where SRO is the solder resist opening, SRR is a solder registration for the manufacturing process, and X is a function of a thickness of the exposed sidewall of the contact pad. The value of X ranges from 5 to 20 microns. The solder bump wets the exposed sidewall of the contact pad and substantially fills an area adjacent to the exposed sidewall. The contact pad can be made circular, rectangular, or donut-shaped.
申请公布号 US2010244245(A1) 申请公布日期 2010.09.30
申请号 US20100813335 申请日期 2010.06.10
申请人 STATS CHIPPAC, LTD. 发明人 PENDSE RAJENDRA D.;KIM YOUNGCHEOL;LEE TAEKEUN;NA GUICHEA;KIM GWANGJIN
分类号 H01L23/498 主分类号 H01L23/498
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