发明名称 Using Electric-Field Directed Post-Exposure Bake for Double-Patterning (D-P)
摘要 The invention provides a method of processing a substrate using Double-Patterning (D-P) processing sequences and Electric-Field Enhanced Layers (E-FELs). The D-P processing sequences and E-FELs can be used to create lines, trenches, vias, spacers, contacts, and gate structures using a minimum number of etch processes.
申请公布号 US2010248152(A1) 申请公布日期 2010.09.30
申请号 US20090415505 申请日期 2009.03.31
申请人 TOKYO ELECTRON LIMITED 发明人 SCHEER STEVEN;SOMERVELL MARK
分类号 G03F7/20 主分类号 G03F7/20
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