发明名称 DELAY GENERATION CIRCUIT, AND CONSTANT CURRENT SOURCE CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a delay generation circuit which depends on only the threshold of a transistor and the amount of current, and to provide a constant-current source employing the delay generating circuit. SOLUTION: A delay generation circuit comprises: a PMOS transistor (PMOSTr) 104a which inputs a control voltage from its gate terminal and generates a reference current; a PMOSTr 105h and operational amplifier 106 for holding the voltage applied to a drain of the PMOSTr 104a; a PMOSTr 105a for supplying the same current IS as the reference current to the PMOSTr 104a; a plurality of PMOSTr 105b-105g each for generating a proportional current to the current that flows to the PMOSTr 105a; and NMOSTr 104b-104g open-drain connected with the PMOSTr 105b-105g. The NMOSTr 104b-104g are connected over multi-stages, a clock signal is inputted to the gate terminal of the NMOSTr 104b, and a delay signal is outputted from the drain of a second or more even-numbered N transistor. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010220178(A) 申请公布日期 2010.09.30
申请号 JP20090067749 申请日期 2009.03.19
申请人 ASAHI KASEI ELECTRONICS CO LTD 发明人 NAKANISHI JUNYA
分类号 G05F3/24;H03F3/345;H03K5/13 主分类号 G05F3/24
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