| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To achieve the reduction of power consumption in a data storage device. <P>SOLUTION: When determining that conditions of shifting a DRAM 101 to a refresh mode are established, a power saving control circuit 213 of a DRAM controller 208 fixes the state of a signal output to each of data signal lines configuring a DRAM bus 115 to a Low level, and stops the supply of a reference voltage to each of the data signal lines configuring the DRAM bus 115 by a TV power source 106. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
