Clock signal generation circuit for reducuing current consumption, and semiconductor device having the same

摘要

In an example embodiment, the semiconductor device includes a clock signal generation circuit. The clock signal generation circuit is configured to generate at least one control clock signal in response to an external clock signal and a read command signal. The clock signal generation circuit includes a plurality of delay circuits, and the clock signal generation circuit is configured to selectively disable at least one of the plurality of delay circuits to reduce power consumption.