发明名称 CIRCUIT, CONTROL SYSTEM, CONTROL METHOD, AND COMPUTER-READABLE RECORDING MEDIUM IN WHICH PROGRAM IS RECORDED
摘要 <p>A circuit able to achieve high frequency tracking performance while satisfying jitter/wander suppression performance. The circuit controls the loop gain of a PLL means (100) according to the results of processing a jitter/wander component and a frequency change state (300) based on the phase comparison data of the PLL means (100). Said PLL means (100) is a means for reproducing an SDH (Synchronous Digital Hierarchy) signal or Ethernet signal from an OTN (Optical Transport Network) signal.</p>
申请公布号 WO2010110184(A1) 申请公布日期 2010.09.30
申请号 WO2010JP54746 申请日期 2010.03.15
申请人 NEC CORPORATION;TAKAHASHI, MASAYUKI;YOSHIHARA, TOMOKI 发明人 TAKAHASHI, MASAYUKI;YOSHIHARA, TOMOKI
分类号 H03L7/107;H03L7/08;H03L7/093 主分类号 H03L7/107
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