| 摘要 |
An resistor string digital-to-analog converter (DAC) that includes elements to compensate for resistor ladder loading, and/or to provide compensation for loading such as via switch current cancellation. The approach reduces output voltage sensitivity to switch resistances while also reducing INL and DNL errors. Additional resistor loops are optionally disposed at the top and bottom of one or more further segments to provide Nth order resistive current cancellation.
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