METHOD, APPARATUS AND SYSTEM OF PARALLEL IC TEST

摘要

PURPOSE: An integrated circuit parallel test method, an apparatus and a system thereof are provided to reduce a time required for performing mass production without increase of the number of channels. CONSTITUTION: A test signal is inputted(202). A parallel test is performed with respect to device-under-test(DUT)(203). The result of the test with respect to the DUT is randomly extracted. The extracted result is compared with an expected result(205). A final test result is generated with data related to the position of the DUT(206). The position of the DUT and the test result are outputted(207).