发明名称 Chaining direct memory access data transfer operations for compute nodes in a parallel computer
摘要 Methods, systems, and products are disclosed for chaining DMA data transfer operations for compute nodes in a parallel computer that include: receiving, by an origin DMA engine on an origin node in an origin injection FIFO buffer for the origin DMA engine, a RGET data descriptor specifying a DMA transfer operation data descriptor on the origin node and a second RGET data descriptor on the origin node, the second RGET data descriptor specifying a target RGET data descriptor on the target node, the target RGET data descriptor specifying an additional DMA transfer operation data descriptor on the origin node; creating, by the origin DMA engine, an RGET packet in dependence upon the RGET data descriptor, the RGET packet containing the DMA transfer operation data descriptor and the second RGET data descriptor; and transferring, by the origin DMA engine to a target DMA engine on the target node, the RGET packet.
申请公布号 US7805546(B2) 申请公布日期 2010.09.28
申请号 US20070829325 申请日期 2007.07.27
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 ARCHER CHARLES J.;BLOCKSOME MICHAEL A.
分类号 G06F13/28;G06F13/00;G06F15/16;G06F15/167 主分类号 G06F13/28
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