RELIABILITY EVALUATION CIRCUIT AND RELIABILITY EVALUATION SYSTEM
摘要
PURPOSE: A reliability evaluation circuit and a reliability evaluation system are provided to reduce a time for evaluating the reliability by applying stress voltages with a plurality of different voltage levels to a plurality of device units. CONSTITUTION: A stress voltage generating block(110) outputs a plurality of stress voltages with different voltage levels through a plurality of first input/output(IO) terminals. A stress device array(120) connects one terminal with one of the first IO terminals. The other terminal of the stress device array is connected with one of second IO terminals. A plurality of device units is arranged in a matrix shape.
申请公布号
KR20100103303(A)
申请公布日期
2010.09.27
申请号
KR20090021865
申请日期
2009.03.13
申请人
SAMSUNG ELECTRONICS CO., LTD.
发明人
KWON, SANG JIN;LEE, JAE HOON;KANG, YONG HA;LEE, JONG WON