发明名称 CIRCUIT DESIGN PROGRAM, CIRCUIT DESIGN METHOD, AND CIRCUIT DESIGN DEVICE
摘要 PROBLEM TO BE SOLVED: To easily and reliably extract a synchronizing reset signal. SOLUTION: A domain extraction means 2 extracts a domain of a signal as a candidate of a synchronizing reset signal of a sequential circuit to be designed. For example, in a circuit 5 shown in a Fig.1, the signal is back traced from an enable terminal of a D flip flop 6, and reaches an external input terminal. The signal (Clear) of the terminal is extracted as a domain. A measurement means 3 measures a signal value to be input to the sequential circuit by changing the logic of the extracted domain signal. In the circuit 5 shown in the Fig.1, a signal value to be input to the D flip flop 6 is measured by changing the logic of the signal (Clear). A synchronizing reset determination means 4 determines whether or not there exists a synchronizing reset signal on the basis of the signal value measured by the measurement means 3. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010211550(A) 申请公布日期 2010.09.24
申请号 JP20090057307 申请日期 2009.03.11
申请人 FUJITSU SEMICONDUCTOR LTD 发明人 MATSUURA TAKASHI;SEKI YUKIE;ITAYA KOICHI
分类号 G06F17/50 主分类号 G06F17/50
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