| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock wiring method which reduces variation in a timing margin for data transmission between flip-flops even if OCV (on-chip variation) exists. Ž<P>SOLUTION: On the basis of layout data for which cell arrangement is completed, a timing margin for a clock signal for data transmission between flip-flops each having a data path is computed, and two flip-flops are combined in ascending order of the timing margin to generate a flip-flop pair. Thereafter, partial clock wiring is wired between the flip-flops of each flip-flop pair, an equi-delay point to two flip-flops of the connection destination is obtained on the partial clock wiring, and a clock tree is generated with the equi-delay point as a final branch point. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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