| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory control apparatus which improves efficiency of data transfer. SOLUTION: A refresh controller 106A includes a pulse-generating circuit 131 for generating the second request signal which requests refresh at a period necessary for refreshing a DRAM 105, and a variations-predicting circuit 132 for generating the first request signal which requests refresh, when the number of data transfer requests in the hereafter is predicted to increase based on the counted value of the data transfer requests and the trend in its variation. An arbitrator 103 arbitrates the request signals, in the order of priority among a first request signal, second request signal and data transfer request. COPYRIGHT: (C)2010,JPO&INPIT
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