| 摘要 |
An address generator of a communication data interleaver and a communication data decoding circuit are provided. The address generator includes a first operation unit and a second operation unit. The first operation unit receives a first parameter and a first operation result. The first operation unit performs a recursive operation according to the first parameter and the first operation result and outputs the first operation result. The second operation unit receives the first operation result, a second operation result, and a second parameter. According to a transmission mode signal, whether the second operation unit generates a second operation result is determined by performing a recursive operation according to the first operation result, the second parameter, and the second operation result, or by calculating the first operation result and the second parameter.
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