发明名称 Method, apparatus and system of parallel IC test
摘要 A method, apparatus and system for integrated circuit testing, wherein a plural number of devices under test (DUTs) and a plural number of comparison apparatuses are placed on a common substrate. The DUTs all operate under the same input stimulation and each produce its own operation output. The outputs are compared by the comparison apparatuses to generate comparison characteristics which are used to filter-out the failed devices. This invention lowers the testing cost, shortens time to product mass-production, and lowers the miss rate of failed devices passed as good ones.
申请公布号 US2010237891(A1) 申请公布日期 2010.09.23
申请号 US20100659768 申请日期 2010.03.19
申请人 SHANGHAI XINHAO (BRAVECHIPS) MICRO ELECTRONICS CO. LTD. 发明人 LIN KENNETH CHENGHAO;GENG HONGXI;REN HAOQI;ZHANG BINGCHUN;ZHEN CHANGCHUN
分类号 G01R31/02 主分类号 G01R31/02
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