| 摘要 |
A low current comparator with programmable hysteresis is disclosed that uses a ratio of latch intrinsic (internal) latch capacitance and capacitance of a sample capacitor to adjust hysteresis. In some implementations, the comparator includes a switch capacitor sampling stage coupled to a dynamic latch output stage. Depending on an output state (0 or 1) of the comparator, hysteresis is generated by adding or subtracting a first charge stored in the latch intrinsic capacitance to or from a second charge stored in the sampling capacitor. The ratio of latch intrinsic capacitance and the capacitance of the sampling capacitor can be adjusted to trim hysteresis value. The hysteresis function does not require additional capacitors or additional logic.
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