| 摘要 |
<p>A system for implementing waveform processing in a software defined radio (SDR) includes a scaleable array processor having a plurality of micro-engines (MEs) interconnected by a two dimensional topology. Each micro-engine includes multiple FIFOs for interconnecting to each other in the two dimensional topology. One micro-engine communicates with another adjacent micro-engine by way of the respective FIFOs. The micro-engines are dedicated to predetermined algorithms. The two dimensional topology includes an array of NxM micro-engines interconnected by the multiple FIFOs. The NxM are integer numbers of rows and columns, respectively, in the array of micro-engines. The micro-engines are dedicated to baseband processing of data for RF transmission or RF reception.</p> |
