CLOCK GENERATION CIRCUIT AND SIGNAL REPRODUCTION CIRCUIT USING THE SAME

摘要

Provided is a clock generation circuit which performs a phase control in a wide range with a low power consumption. Provided also is a signal reproduction circuit using the clock generation circuit. A counter circuit (a divider circuit) CUNT_BLK1 is provided on a feedback route of a PLL circuit while a variable delay circuit VDLY1 is arranged at the latter stage thereof, so that the phase of the clock signal CLKout can be rotated. The VDLY1 has, for example, a delay amount control width corresponding to one cycle time (C1) of CLKout. Here, if the delay amount by the VDLY1 reaches a maximum value (max), the CUNT_BLK1 shifts the phase of the output clock signal CLKct by (C1), and the VDLY1 resets the delay amount to a minimum value (0). Thus, the VDLY1 can further control the delay amount. As a result, the phase of the CLKout can be rotated.