发明名称 |
Cached Memory System and Cache Controller for Embedded Digital Signal Processor |
摘要 |
A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core.
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申请公布号 |
US2010235578(A1) |
申请公布日期 |
2010.09.16 |
申请号 |
US20100792865 |
申请日期 |
2010.06.03 |
申请人 |
QUALCOMM INCORPORATED |
发明人 |
SIH GILBERT CHRISTOPHER;SAKAMAKI CHARLES E.;HSU DE D.;WEI JIAN;HIGGINS RICHARD |
分类号 |
G06F12/08;G06F12/00;G06F13/28 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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