| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide, in a small area, a semiconductor integrated circuit which can suppress fluctuation in delay time of a delay circuit due to variation in characteristics of transistors, is further resistant to variations in processing during a manufacturing process and is excellent in layout expandability. <P>SOLUTION: A P-type MOS transistor MP11 and two or more N-type MOS transistors MN11 and MN12 connected in series between a first power source VDD and a second power source (ground power source) are provided. An input terminal IN is connected to a gate terminal of the P-type MOS transistor MP11 and gate terminals of the N-type MOS transistors MN11 and MN12. Further, one or more capacitive elements C1 connected with an output terminal OUT serving as a contact between the P-type MOS transistor MP11 and the N-type MOS transistor MN11 are provided. Driving ability of the P-type MOS transistor MP11 is structured to be larger than total driving ability of the two or more N-type MOS transistors MN11 and MN 12 connected in series. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
