发明名称 DUMMY FILL TO REDUCE SHALLOW TRENCH ISOLATION (STI) STRESS VARIATION ON TRANSISTOR PERFORMANCE
摘要 PROBLEM TO BE SOLVED: To provide dummy pattern design for reducing the performance drift of a MOS device caused by a difference of stress applied on the MOS device. SOLUTION: A method of forming an integrated circuit structure on a chip includes extracting an active layer from the design of the integrated circuit structure and forming a guard band conforming to the shape of the active layer. The guard band surrounds the active layer, and is spaced from the active layer at a first spacing in the X-axis direction and at a second space in the Y-axis direction. Furthermore, the guard method includes steps for removing any part of the guard band that violates design rules, removing convex corners of the guard band, and adding dummy diffusion patterns into the remaining space of the chip outside the guard band. The first and second spaces can be specified to be identical to spaces in the Spice model characterization of the integrated circuit structure. The dummy diffusion patterns with different granularities can be added so that diffusion density is substantially uniform over the chip. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010206198(A) 申请公布日期 2010.09.16
申请号 JP20100042808 申请日期 2010.02.26
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD 发明人 CHERN CHAN-HONG
分类号 H01L21/82;H01L21/76;H01L21/8234;H01L27/088 主分类号 H01L21/82
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