发明名称 SOFTWARE ERROR INCIDENCE CALCULATION DEVICE AND CALCULATION METHOD
摘要 <P>PROBLEM TO BE SOLVED: To provide a software error incidence calculation method which calculates the incidence of software errors with a high precision. Ž<P>SOLUTION: The software error incidence calculation method is a method for calculating the incidence of software errors in a semiconductor integrated circuit and includes: a distance calculation step of calculating, as a limited distance, a distance along a well wherein a parasitic bipolar effect may occur, beginning at a diffusion layer wherein a funneling phenomenon has occurred; and a step of determining the occurrence of a software error in a cell including an off-state transistor, in the case where the off-state transistor exists within the limited distance along the well from the diffusion layer wherein the funneling phenomenon has occurred due to the passage of charged particles. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2010205048(A) 申请公布日期 2010.09.16
申请号 JP20090050765 申请日期 2009.03.04
申请人 RENESAS ELECTRONICS CORP 发明人 TANAKA KATSUHIKO
分类号 G06F17/50 主分类号 G06F17/50
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