| 摘要 |
<p>Disclosed is a decoding device which is provided with: multi-level difference cyclic substitution means (106) that performs multi-level cyclic substitution; address management means (104) that manages the address of a cumulative LLR memory (101); received value alignment means (103) that performs record generation when writing received values to the cumulative LLR memory (101); and control means (110) that generates a parameter for controlling these respective means from the information of a parity checking matrix and the current cyclic substitution size. The address management means (104) controls the read address of the cumulative LLR memory (101) based on the read start address from the cumulative LLR memory (101) corresponding to the row block. After commencement of reading of a row block, the control means (110) generates a read start address in the next decoding processing of this row block, and holds this in the address management means (104). In this way, it is possible to provide a decoding device for pseudo-cyclic LDPC code consisting of cyclically substituted matrix blocks of arbitrary cyclic substitution size with a fixed degree of parallelism, wherein the size of the device can be reduced.</p> |
