发明名称 BUS ENHANCED NETWORK ON CHIP
摘要 <p>A system that includes multiple modules of an integrated circuit; a network on chip that is coupled to the multiple modules; a bus, coupled in parallel to the network on chip to the multiple modules; wherein a latency of the bus is lower and more predictable than an average latency of the network of chip.</p>
申请公布号 EP2227749(A2) 申请公布日期 2010.09.15
申请号 EP20080856957 申请日期 2008.12.07
申请人 TECHNION RESEARCH & DEVELOPMENT FOUNDATION LTD. 发明人 CIDON, ISRAEL;KOLODNY, AVINOAM;WALTER, (ZIGMOND) ISASK'HAR
分类号 G06F15/78 主分类号 G06F15/78
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