| 摘要 |
PURPOSE: An interface device for communication between processors and a communication system are provided to supply a flexible, symmetrical, and standardized interface for communication between a host processor and a sub processor. CONSTITUTION: The second layer(L2) manages a logical channel state and a physical channel state of a hardware channel for communication with a counterpart processor. The second layer transceives data with the counterpart processor based on the logical channel state and physical channel state. The third layer(L3) comprises one or more hardware interface APIs. The hardware interface API connects the interface device with hardware of the processor based on control by the second layer.
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