发明名称 |
System and method for providing more logical memory ports than physical memory ports |
摘要 |
Some embodiments provide for a method of mapping a user design to a configurable integrated circuit (IC). The method is for a configurable IC that implements a user design with an associated user design clock cycle. The IC operates on a sub-cycle clock that has multiple sub-cycle periods within a user period of the user design clock cycle. The method identifies multiple port accesses to a first multi-port memory defined in the user design. The accesses are in a single user design clock cycle. The method maps the multiple port accesses to the first multi-port memory to multiple physical-port memory accesses to a second physical-port memory in the configurable IC during multiple sub-cycles associated with a single user design clock cycle.
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申请公布号 |
US7797497(B1) |
申请公布日期 |
2010.09.14 |
申请号 |
US20060371214 |
申请日期 |
2006.03.08 |
申请人 |
TABULA, INC. |
发明人 |
SCHMIT HERMAN;TEIG STEVEN;HUTCHINGS BRAD |
分类号 |
G06F13/00 |
主分类号 |
G06F13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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