发明名称 |
Systems for implementing SDRAM controllers, and buses adapted to include advanced high performance bus features |
摘要 |
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to encode a priority of a plurality of input signals. The second circuit may be configured to generate the plurality of input signals in response to one or more signals received from each of a plurality of ports. The apparatus generally provides dynamic priority arbitration for the plurality of ports.
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申请公布号 |
US7797467(B2) |
申请公布日期 |
2010.09.14 |
申请号 |
US20060520219 |
申请日期 |
2006.09.13 |
申请人 |
LSI CORPORATION |
发明人 |
WORRELL FRANK;AU KEITH D. |
分类号 |
G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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