| 摘要 |
A semiconductor memory for maintaining a word line driving voltage includes a cell array and a sense amplifier adjacent to the cell array. A dummy cell is formed at a peripheral portion of the cell array in such a manner that a dummy bit line and a word line intersect. A control circuit switches the connection state between a first section of the dummy bit line passing through the cell array and a second section of the dummy bit line passing through the sense amplifier. The connection state switches according to the operation mode of the cell array. The dummy bit line is floated when the operation mode is an active mode and a precharge voltage is provided to the dummy bit line when the operation mode is a precharge mode.
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