DELAY LOCKED LOOP AND SEMI-CONDUCTOR MEMORY DEVICE USING THE SAME

摘要

PURPOSE: A delay locked loop circuit and a semiconductor memory device thereof are provided to select an initially locked signal by comparing the phase of a non-inverting/inverting regeneration clock signal with the phase of a received clock signal. CONSTITUTION: A variable delay line part(120) generates a regeneration clock signal which follows the phase of a received clock signal in response to a delay control signal. A phase detecting part(130,150) detects the phase difference of the regeneration clock signal, an inverting regeneration clock signal which inverts the regeneration clock signal, or the received clock signal. The phase detecting part outputs a first and a second phase difference detection signal. An inversion control part(160) outputs an inversion control signal which determines the inversion state of the received clock signal based on the first and the second phase difference detection signal. An inversion part(170) selectively outputs the regeneration clock signal or the inverting regeneration clock signal based on the inversion control signal.