SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

摘要

In a semiconductor integrated circuit device, different power area pad arrangements are used in the periphery portion P and the center portion M of a chip (101).  That is, in the 2-column 2-row periphery portion P of the chip (101), VDD area pads (103) connected to high-voltage power VDD and GND area pads (104) connected to the ground power GND are alternately arranged in both of the row direction and the column direction.  Moreover, in the center portion M of the chip (101), the same VDD area pads (103) or the GND area pads (104) are continuously arranged in the row direction while the VDD area pads (103) and the GND area pads (104) are alternately arranged in the column direction.  The power area pad arrangement enables suppression of voltage drop.