| 摘要 |
<P>PROBLEM TO BE SOLVED: To synchronize a decision signal, being output at the operating test of a semiconductor memory device, with a clock signal. Ž<P>SOLUTION: The semiconductor memory device includes: a decision circuit 60 for deciding an error in a read data read out from a memory cell array 50, so as to generate a decision signal E; and an I/O circuit 54 for externally outputting the read data or the decision signal via a data input/output terminal DQ. In a normal operating mode, the I/O circuit 54 externally outputs the read data at first timing, while in a test mode, the I/O circuit outputs the decision signal with delay at second timing. The difference of the first and the second timing is an integer multiple of a clock signal cycle. As such, since timing control is internally made to make the decision signal output timing delayed from the read data output timing, the decision signal in the test mode is output correctly. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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