发明名称 TIMING VERIFICATION METHOD AND TIMING VERIFICATION APPARATUS
摘要 PROBLEM TO BE SOLVED: To provide a timing verification method and an apparatus for the same, capable of executing timing verification on timing verification-required paths necessary for timing verification without any omission. SOLUTION: The timing verification method includes: a timing verification-required path-extracting process which analyzes connection information of an integrated circuit and extracts a plurality of timing verification-required paths; a first timing analysis process which obtains signal delay-related information on the plurality of timing verification-required paths based on representative timing verification conditions including manufacturing conditions and operation conditions of the integrated circuit, and which calculates the signal delay time of the plurality of timing verification-required paths from the delay-related information to perform timing analysis of signals propagating through the plurality of timing verification-required paths; a process for inputting specific determination conditions from the plurality of timing verification-required paths; a specific path selecting process which selects some paths corresponding to the specific determination conditions as specific paths; and a second timing analysis process which performs timing analysis of signals propagating through the specific paths. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010198526(A) 申请公布日期 2010.09.09
申请号 JP20090045202 申请日期 2009.02.27
申请人 FUJITSU SEMICONDUCTOR LTD 发明人 FUJITA MIYAKO;WAKITA MAKOTO;HOSONO TOSHIKATSU
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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