DUTY CYCLE CORRECTOR PREVENTING EXCESSIVE DUTY CYCLE CORRECTION IN LOW-FREQUENCY DOMAIN

摘要

Provided is a duty cycle corrector including a low frequency detector detecting whether an input clock signal frequency is less than or greater than a predetermined frequency. If less than, a common mode control circuit controlling a common mode of a duty cycle correction amplifier amplifying the input clock signal is disabled. The duty cycle corrector may include a column address strobe (CAS) latency determination unit that determines whether a CAS latency is greater than or less than a predetermined value instead of the low frequency detector.