发明名称 METHOD FOR INSPECTING OTP MEMORY, METHOD FOR MANUFACTURING THE OTP MEMORY, THE OTP MEMORY, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a method for predicting and eliminating an OTP (on time programmable) memory of a high write-failure rate, a method for setting a voltage which is optimal for writing on a memory element, and an OTP memory to which the methods are applicable. SOLUTION: In the OTP memory having a memory cell array and an inspection circuit, the OTP memory with a low failure rate is provided, by predicting the failure rate of the memory element of the memory cell array from a cumulative frequency distribution of a short circuit rate, with respect to a writing voltage of the memory element included in the inspection circuit, and eliminating a substrate with a high failure rate. In the OTP memory where a shape of the cumulative frequency distribution is substantially linear, the OPT memory of reduced power consumption is provided, by estimating the value of a voltage optimal for writing of the memory element by using the cumulative frequency distribution, and setting a voltage optimal for writing of the memory element. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010198693(A) 申请公布日期 2010.09.09
申请号 JP20090043773 申请日期 2009.02.26
申请人 SEMICONDUCTOR ENERGY LAB CO LTD 发明人 SAITO TOSHIHIKO;YOSHIZUMI KENSUKE;GOTO YUMIKO
分类号 G11C29/56 主分类号 G11C29/56
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