发明名称 |
Fully associative texture cache having content addressable memory and method for use thereof |
摘要 |
A graphics processing system including a cache memory circuit coupled to the graphics processor and the address and data busses for storing graphics data according to a respective address. The cache memory includes first and second memories coupled together by a plurality of activation lines. The first memory has a corresponding plurality of address detection units to store addresses and provide activation signals in response to receiving a matching address. The second memory includes a corresponding plurality of data storage locations. Each data storage location is coupled to a respective one of the plurality of address storage locations by a respective activation line to provide graphics data in response to receiving an activation signal from the respective address storage location.
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申请公布号 |
US7791612(B2) |
申请公布日期 |
2010.09.07 |
申请号 |
US20040931375 |
申请日期 |
2004.08.31 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
MUNSHI AAFTAB |
分类号 |
G06T11/40;G06F12/06;G06T1/20;G06T1/60;G06T15/00;G09G5/36 |
主分类号 |
G06T11/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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