发明名称 Method and system for designing a timing closure of an integrated circuit
摘要 Aspects for designing a timing closure of an integrated circuit include instantiating a minimum repeater between at least one block and a corresponding blockage if an interconnect crosses the corresponding blockage and according to a drive of the blockage. The aspects further include instantiating one or more smallest repeaters between at least one pair of connected blocks depending upon a drive of a corresponding interconnect, the instantiation of the smallest repeater being based on pre-determined criteria.
申请公布号 US7793254(B2) 申请公布日期 2010.09.07
申请号 US20070826723 申请日期 2007.07.18
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 EICHENSEER PATRICK JOHN;LEWELLING RICKY;SADI ZIAD
分类号 G06F17/50 主分类号 G06F17/50
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