发明名称 Multi-tap decision feedback equalizer (DFE) architecture eliminating critical timing path for higher-speed operation
摘要 A decision feedback equalizer (DFE) and method include summer circuits to add a dynamic feedback signal representing a dynamic feedback tap to a received input and to speculate on a speculative tap. Data slicers are configured to receive outputs of the summer circuits and sample the outputs of the summer circuits. First multiplexers are included, each of which is configured to receive a first input from a corresponding data slicer. Second multiplexers are included, each of which is configured to receive an output of a plurality of the first multiplexers. The second multiplexers have an output fed back to a second input of the first multiplexers, and the second multiplexer output is employed to provide a select signal for a second multiplexer on a different section of the DFE and to drive the dynamic feedback signal to a summer circuit on a same section of the DFE.
申请公布号 US7792187(B2) 申请公布日期 2010.09.07
申请号 US20070848477 申请日期 2007.08.31
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 BULZACCHELLI JOHN F.
分类号 H03K5/159 主分类号 H03K5/159
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