| 摘要 |
A system for remotely synchronizing a majority voter circuit. The system comprises a first processor for generating a data packet and a synchronization pulse wherein the synchronization pulse indicates a predetermined bit location in the data packet. The system further comprises a plurality of second processors communicatively coupled to the first processor. Each of the plurality of second processors has a register, and each of the plurality of second processors receives the data packet and the synchronization pulse, and stores the data packet and the synchronization pulse in its respective register. A voting processor is communicatively coupled to each of the plurality of second processors. The voting processor receives at least a portion of the data packet from each of the plurality of processors, and utilizes the synchronization pulse to align each of the received portions of the data packets, according to the synchronization pulse prior to voting.
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