发明名称 Integration of high k gate dielectric
摘要 Methods are provided herein for forming electrode layers over high dielectric constant (“high k”) materials. In the illustrated embodiments, a high k gate dielectric, such as zirconium oxide, is protected from reduction during a subsequent deposition of silicon-containing gate electrode. In particular, a seed deposition phase includes conditions designed for minimizing hydrogen reduction of the gate dielectric, including low hydrogen content, low temperatures and/or low partial pressures of the silicon source gas. Conditions are preferably changed for higher deposition rates and deposition continues in a bulk phase. Desirably, though, hydrogen diffusion is still minimized by controlling the above-noted parameters. In one embodiment, high k dielectric reduction is minimized through omission of a hydrogen carrier gas. In another embodiment, higher order silanes, aid in reducing hydrogen content for a given deposition rate.
申请公布号 US7790556(B2) 申请公布日期 2010.09.07
申请号 US20050148721 申请日期 2005.06.09
申请人 ASM AMERICA, INC. 发明人 POMAREDE CHRISTOPHE F.;GIVENS MICHAEL E.;SHERO ERIC J.;TODD MICHAEL A.
分类号 C23C16/24;H01L21/336;C23C16/02;C30B25/02;H01L21/20;H01L21/205;H01L21/28;H01L21/285;H01L21/3205;H01L21/4763;H01L21/763;H01L21/8242;H01L27/108;H01L29/423;H01L29/49;H01L29/51;H01L29/78;H01L29/786;H01L31/18;H01L31/20 主分类号 C23C16/24
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