发明名称 VOLTAGE POLARITY DISCRIMINATION CIRCUIT AND ELECTRICAL LOAD MEASURING CIRCUIT
摘要 <p>A voltage polarity discrimination circuit (1) is provided with an integration circuit (10), a switch (SW0), and a time measuring circuit (12). The integration circuit (10) is constructed by using an operational amplifier circuit (100) having an input offset voltage (Vosa) which is greater than the maximum value or less than the minimum value of the input voltage (Vin) of the integration circuit (10). The switch (SW0) switches the input voltage (Vin) to the integration circuit (10) to the voltage of the polarity discrimination target (voltage Rin between the terminals) or to a reference voltage (GND). The time measuring circuit (12) measures the time until the output voltage (V10) of the integration circuit (10) reaches a set voltage. The polarity of the input voltage (Vin) to the integration circuit (10) is discriminated on the basis of the measurement result.</p>
申请公布号 WO2010098090(A1) 申请公布日期 2010.09.02
申请号 WO2010JP01247 申请日期 2010.02.24
申请人 PANASONIC CORPORATION;INOUE, ATSUO;MATSUNO, NORIAKI 发明人 INOUE, ATSUO;MATSUNO, NORIAKI
分类号 G01R19/14;G01R31/36 主分类号 G01R19/14
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