发明名称 APPARATUS, METHOD AND PROGRAM FOR LAYOUT DESIGN OF SEMICONDUCTOR DEVICE
摘要 <P>PROBLEM TO BE SOLVED: To solve a problem of chip size increase when performing power supply separation processing. Ž<P>SOLUTION: The problem of chip size increase can be solved by a layout design apparatus for a semiconductor device having a cell data storage and a separation processing unit. The cell data storage stores cell data of each cell in a semiconductor device having a structure wherein a plurality of cells are adjacently continued. The separation processing unit processes cell data and separates metal wiring provided over a plurality of cells between the cells in accordance with a design standard of the semiconductor device. The separation processing unit has an extension/shortening unit and an inversion unit. The extension/shortening unit is part of the metal wiring for each cell data. It extends one end of a metal portion to be arranged inside a cell frame of each cell and shortens the other end in the same direction as an extending direction of the one end. The inversion unit performs mirror inversion for an arbitrary cell having a metal portion which is extended and shortened by the extension/shortening unit so that the extended one end and the other shortened end are replaced. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2010192740(A) 申请公布日期 2010.09.02
申请号 JP20090036399 申请日期 2009.02.19
申请人 RENESAS ELECTRONICS CORP 发明人 TANAKA NAOHIRO
分类号 H01L21/82;G06F17/50 主分类号 H01L21/82
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