| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce output noise and increase a response speed of an output buffer circuit. <P>SOLUTION: In a case where an output voltage VOUT changes from a ground voltage VSS to the inversion voltage VL of NOR, and in a case where the output voltage changes from a power supply voltage VDD to the inversion voltage VH of NAND, since both of two MOS transistors control the output voltage VOUT, the slew rate of the output voltage VOUT becomes steep. Thus, the response speed of an output buffer circuit becomes faster. Further, in such a case that the output voltage VOUT changes in the vicinity of a voltage (VDD/2) other than these cases, since only one MOS transistor controls the output voltage VOUT, the slew rate of the output voltage VOUT becomes gentle. Thus, since the response speed of the output buffer circuit becomes slow, output noise is reduced. <P>COPYRIGHT: (C)2010,JPO&INPIT |
