GENERATION OF A LOW JITTER CLOCK SIGNAL

摘要

Systems and methods for generation of a low jitter clock signal for wireless circuits are disclosed. In an implementation, the system includes a wireless circuit powered by a first power supply and a low jitter clock (LJC) generator powered by a second power supply. The LJC generator provides at least one clock signal to the wireless circuit. The system further includes an LJC driver circuit including a clock buffer powered by the first power supply and a receive buffer powered by the second power supply.